A Parallel VLSI Architecture for Two-Dimensional Discrete Periodized Wavelet Transfrom

Abstract

Based on the two-dimensional (2-D) operator correlation algorithm, a nowel approach of VLSI architecture design called non-separate architecture is developed to implement the (2-D) discrete periodized wavelet transfrom (DPWT) in this paper. The main features of the architecture are short-time latency, short bit lengthe request, and fast to derive intact octave band components for the purpose of three funcitional units: parallel multipiers, data accumulator, and input data controller. The architecture is in the nature of a parallel processing structure.As a consequence, its parallel modularity markes it well suited for VLSI implementation. A detailed analysis of finite precision performance on the accuracy of 2-D filter conefficients, 2-D DPWT coefficients, and the reconstructed data is also pressented in this paper. The overall architecture has been successfully simulated with 21 data bits of Verilog behavioral model simulation to confirm the feasibility.