A Study for Carry Propagation Delay of Digital Ratioed Compressors

Abstract

Inner product calculations are often required in digital neural computing. The critical of the inner product of two binary vectors is the carry propagation delay generated from individual product terms. In this work, a hierarchical structure of ratioed compressor building blocks is proposed, and the carry propagation delay estimation of these formula is obtained, which leads a minimal delay of calculation. The theoretical derivation and Verilog simulation both indicate that the 3-2 compressor might be an ideal candidate for the basic building blocks used in digital hardware realization of the inner product computation.