Design, Implementation and Error Analysis of Redundant CORDIC Processors for Fast Vector Rotation and Trigonometric Function Evaluation

Abstract

A new high-speed redundant CORDIC processor is designed and implemented based on the double rotation method, which truns out to be the two-dimenssional(2-D) Householder CORDIC, a special case of the generalized Householder CORDIC in the 2-D Euclidean vector space. The new processor has the advantages of regular structure and high throughput rate. The pipelined structure with rediz-2 signed-digit(SD) redundant arithmetic is adopted to reduce the carrypropagation delay of the adders while the digit-serial structure alleviates the burden of the hardware cost and I/O requirement. Compared to previously proposed designs, the new CORDIC processor preserves the constant scaling factor, an important merit of the original CORDIC, and thus does not require any complicated division or square-toot operations for variable scaling factor calculation. Practical VLSI chip implementation of the fired-point redundant CORDIC processor using 0.6um standard cell library is given including detailed numerical error analysis.