Design of Parallel Processors for Fast Extraction of Peaks From Multi-Dimensional Data Array

Abstract

Peak detection is needed in many computer applications. For the real-time demand and not to become a bottleneck, this process requires parallel hardware for much faster operation. In this paper, a series of VLSI array processor designs are proposed for various needs of peak detection from multi-dimensional data array. We have designed the row sequential comparator and 3-row delayed comparator to compose a basic pipelined 3 x 3 maximum filter. Based on such module, the 3 x 3 or 5 x 5 pipelined peak detector can be easily configured. The design can be extended to the three-dimensional 3 x 3 x 3 and 5 x 5 x 5 peak detection, detecting local peaks of broader range, or even the cases of higher dimension. To further raise the peak-detection speed, we also propose some array processors to extract peaks (of 3 x 3 range) in parallel, column by column. And once again, our parallel detector design can be extended to the higher dimension and to detect local peaks of broader range.