題名: | PFPC: An Infrastructure for Research on Parallelizing Compilers |
作者: | Yang, Chao-Tung Tseng, Shian-Shyong Fann, Yun-Woei Hsieh, Ming-Huei |
期刊名/會議名稱: | 2000 ICS會議 |
摘要: | As we know, the execution efficiency of a loop can be enhanced if the loop is executed in parallel or partially parallel, like a DOALL or DOACROSS loop. This paper also reports on a practical parallel loop detector (PPD) that is implemented in PFPC on finding the parallelism in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by verifying array subscripts. In addition, a new model by using knowledge-based approach is proposed to exploit more loop parallelisms in this paper. The knowledge-based approach integrates existing loop transformations and loop scheduling algorithms to make good use of their ability to extract loop parallelisms. Two rule-based systems, called the KPLTan d IPLS, are then developed using repertory grid analysis and attribute ordering tables respectively, to construct the knowledge bases. Finally, a runtime technique based on inspector/executor scheme is proposed in this paper for finding available parallelism on loops. Our inspector can determine the wavefronts of a loop with any complex indirected array indexing pattern by building a DEF-USE table. Experimental results show that the new method can handle any complex data dependence pattern that cannot be handled by the previous research. |
日期: | 2006-10-27T02:56:35Z |
分類: | 2000年 ICS 國際計算機會議 |
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