Semantic-Based Load/Store Scheduling for X86 Superscalar Microprocessor

Abstract

For x86 compatible processors, the proportion and latencies of memory accesses are relatively high thus impact the performance of these processors severely. In this paper, we propose a semantic-based load/store scheduling to alleviate these limitations. In x86 architecture, most of the local variables and parameters of a function are stored in stack memory. We find that the addresses of stack accessing operations will be the same if the displacements of these instructions are the same. Therefore, we may track the dependencies and forwarding paths between the stack accessing operations according to the displacement values of the operations. From our simulation results, the speed up of semantic-based load/store scheduling alone can achieve 1.47 compared with the strategy of load bypassing stores with forwarding. While combing this scheduling with selective address/dependency prediction, it can achieve the speed up of 1.70