An Interconnect-Driven Low Power Design Methodology

Abstract

Low power is a significant concern for the today’s ASIC designs. To shorten the design time, it is very important to correctly supply the design environment all the power related information that is necessary. However, the interconnect capacitance estimation is a difficult task during the synthesis stage due to the lack of place and route information. In this paper, we will present an interconnect-driven design methodology. To minimize the iterations between synthesis and layout, the proposed approach is distinctive in that it constructs physical hierarchy during the synthesis stage. Our optimization goal is to minimize the power dissipation of the chip, especially when the system is at the standby mode. Experimental data shows that this design methodology achieved very good results.