A Practical Clock Tree Synthesis Flow

Abstract

In deep sub-micron ear, an ASIC chip may contain millions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important. After conducting many clock tree synthesis experiments, which explore various configuration of clock tree structures and layouts, a guidance for clock tree synthesis is generated. By applying this guidance, the clock tree design procedure is simplified and the design time is shortened. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single clock trees the intra-clock skew is confined within 0.1ns in one design pass for 0.35u CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proven to be an effective method to implement clock trees on ASIC chips.