On the Design and Modeling of a Homogeneous VLIW Architecture

Abstract

Following the advances in semiconductor technology and computer architecture, we can expect that the functional units on a single chip can grow to tens in the future. By considering the trend in microprocessor design, we propose a new type of parallel architecture which combines the features of both ILP and SIMD machines for instruction level parallelism and loop level parallelism, respectively. In order to verify the efficiency of the parallel architecture, we have built an analytical model to explore architecture performance with parallelism ranging from different architecture features. The analytical results show that the inclusion of SIMD type execution can improve the execution of vector loops and gain a speedup of 1.6 over traditional ILP machine. When the execution parallel architecture can still gain speedups in the range of 1.023 to 1.567 depending on ratio variations of vector codes.