Estimation of Delay Due to Overshoot Efficient for CMOS Gates in Binary-Tree Timing Simulation

Abstract

A switch-level timing simulator has the advantage of fast speed and good adaptability for VLSI circuit, but it can not offer more accurate transient waveform information. A new approach for delay estimation is presented which is achieved by two equations：dominant delay equation and error delay equation. Both are derived by surface fitting to approximate the surface that is measured from the actual delay behavior of a CMOS gate.