Evaluating and Improving Variable Length History Branch Predictors

Abstract

With the never ending quest for high performance and cost/power efficient processor design in recent years, how to provide performance on adequate hardware and power budgets has become an important issue. In this paper, we review and evaluate several variable length history branch predictors for high performance processors and propose a modified branch predictor, f-TAGE, to improve critical path delay for highly accurate TAGE (TAgged GEometric history length) branch predictor f-TAGE applies Priority Multiplexer to reduce multi-level gate delays. We analyze and empirically study our proposed scheme along with variable length history prediction schemes, including the Fast Path-Based Neural Branch Predictor (FPB), Piecewise Linear Branch Predictor (PLB) and TAGE as well as Optimized GEometric History Length branch predictor (O-GEHL) with respect to critical path delay, branch prediction accuracy and hardware overhead. It is shown that f-TAGE reduces critical path delay and preserves prediction accuracy at the cost of modest hardware overhead. From our evaluation, the proposed scheme can lower TAGE critical path delay by up to 21% at little hardware overhead.