Design Space Exploration and Construction of an Arbiter Design Model

Abstract

Because of the flourish of multi-processor system-on-a-chips (MPSoCs) and on- or off-chip high-speed networks, how to design an efficient arbiter, although a classical problem, now becomes more and more important. In the past, there were little or no work that thoroughly discussed the functionality, design issues and models of arbiters, which resulted in the inferior arbiter design and usages. Here, we have aimed at exploring the design space and the issues of operating of arbiters, and proposed a new multi-function arbiter design model and classification. With this new design model, we could further know the required key points of arbiter design, and thus have designed an efficient integrated multi-function arbiter that suitable to many different applications. A Round-Robin arbiter based on this model has been designed; to best of our knowledge, it is the fastest and smallest Round-Robin arbiter.