鰭式電晶體矽鰭載子電荷分佈探討及可靠度研究

Abstract

本專題研究FinFET元件在不同鰭寬(10nm與25nm)之電特性研究，經由量測曲線圖:n-type FinFET 在Wfin=10nm與Wfin=25nm時的ID-VD圖、ID-VG圖、IG-VG圖及n-type的VTH - Wfin圖、VTH - Lg圖來分析元件的臨界電壓、次臨界斜率(subthreshold swing，SS)及汲極引發能障下降值(drain induced barrier lowering，DIBL)效應、元件導通電流等基本特性，並比較鰭寬10nm及25nm下double gate n-type FinFET的電性差異，測量結果顯示鰭寬10nm的FinFET其DIBL值與SS值都比鰭寬25nm的小，此結果可得知鰭較窄的元件對於短通道效應有較好的抵抗力。另外，我們在論文中探討元件雜訊對於元件的影響。半導體材料若不是在絕對零度的環境下，導體中的電子或電洞會受到溫度影響，產生隨機的擾動，在元件內發生的雜訊又分為四種:熱雜訊(thermal noise)、產生-復合雜訊(G-R noise)、閃爍雜訊1/f (flicker noise)和散射雜訊(shot noise)，其中我們使用低頻雜訊(low-frequency noise)來分析氧化層陷阱電荷分佈及矽鰭載子電荷分佈，在LFN的分析上，透過實驗求出的數據 α 可得知Fin越窄雜訊曲線斜率會越大，且缺陷分佈於深層氧化層內，同時影響FinFET元件的性能，透過這種方式來探討矽鰭載子分佈與元件的可靠度。

Our study mainly focuses on the electrical characteristics of FinFET at different fin width (10nm and 25 nm).Through the measureable graph : figure ID-VD, figure ID-VG, figure IG-VG with n-type FinFET in Wfin=10nm and Wfin=25nm and the figure VTH - Wfin, figure VTH - Lg of n-type to analyze the threshold voltage, subthreshold swing (SS), and drain induced barrier lowering (DIBL) effect, on-current of device. In addition, to compare the different electrical properties between the fin’s width is10nm and 25nm in the n-type double gate. The results show that the value of DIBL and SS in fin width of 10nm are both smaller than that of 25nm.This result can find out that short-channel effect of the narrow fin width have better immunity. In addition, we discuss the property of the device based on the noise in our study. If Semiconductor material is not in an environment of absolute zero, the electrons and holes in the conductor will be affected by temperature to generate a random disturbance. Noise occurring in the device are divided into four categories: thermal noise, generation-recombination noise, flicker noise 1/f and shot noise. Where we use the low-frequency noise to analyze the distribution of the trap in oxide layer and the distribution of the charge in silicon fin. In the analysis of LFN, the exponent value of α that obtain from the experiment can know that the fin width is more narrow ,then the curve slope of noise more larger and the distribution of the defect are in the deep oxide layer, at the same time, it will affect the performance of FinFET. Though this way to investigate the distribution of charge in silicon fin and the reliability of device.