On Achieving Better Signal Integrity in Area-Array Floorplanning by Minimal Decap Insertion

Abstract

With technology further scaling into deep submicron era, more components can be placed onto one chip (Systemon- chip, SoC). However, the same scaling brings the design difficulties, among which signal integrity is one of the most important issues. Although flip-chip and area-array architectures have been proposed to strengthen the integrity, we still need careful planning in SoC designs. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from overdesign problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during supply noise driven floorplanning in area-array designs. The experimental results are encouraging. Compared with other approaches in [13] and [10], we have inserted enough decap to meet supply noise constraint while others employ more area.