完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Chang-Jiu | |
dc.contributor.author | Peng, Bing-Chia | |
dc.date.accessioned | 2009-08-23T04:42:41Z | |
dc.date.accessioned | 2020-05-25T06:53:37Z | - |
dc.date.available | 2009-08-23T04:42:41Z | |
dc.date.available | 2020-05-25T06:53:37Z | - |
dc.date.issued | 2007-01-26T01:30:22Z | |
dc.date.submitted | 2006-12-04 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/3481 | - |
dc.description.abstract | Due to that different panel module implementations have different characteristics, panel module will affect designs on timing control signals. If we want to implement a new panel module we have to design new timing controller. In this paper, we use Verilog to implement flexible TFT-LCD timing controller. We use EEPROM memory to save associated control timing values, and we can reuse timing controller for different panel modules and reduce design cycle of panel system. Finally, we use XILINX FPGA to verify control timing and use TFT-LCD panel to verify frame rate control algorithm. | |
dc.description.sponsorship | 元智大學,中壢市 | |
dc.format.extent | 6p. | |
dc.format.extent | 3966207 bytes | |
dc.format.mimetype | application/pdf | |
dc.language.iso | zh_TW | |
dc.relation.ispartofseries | 2006 ICS會議 | |
dc.subject.other | Circuit Design | |
dc.title | TFT-LCD Timing Control Based on FPGA | |
分類: | 2006年 ICS 國際計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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ce07ics002006000031.pdf | 3.87 MB | Adobe PDF | 檢視/開啟 |
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