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dc.contributor.authorChen, Chang-Jiu
dc.contributor.authorPeng, Bing-Chia
dc.date.accessioned2009-08-23T04:42:41Z
dc.date.accessioned2020-05-25T06:53:37Z-
dc.date.available2009-08-23T04:42:41Z
dc.date.available2020-05-25T06:53:37Z-
dc.date.issued2007-01-26T01:30:22Z
dc.date.submitted2006-12-04
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/3481-
dc.description.abstractDue to that different panel module implementations have different characteristics, panel module will affect designs on timing control signals. If we want to implement a new panel module we have to design new timing controller. In this paper, we use Verilog to implement flexible TFT-LCD timing controller. We use EEPROM memory to save associated control timing values, and we can reuse timing controller for different panel modules and reduce design cycle of panel system. Finally, we use XILINX FPGA to verify control timing and use TFT-LCD panel to verify frame rate control algorithm.
dc.description.sponsorship元智大學,中壢市
dc.format.extent6p.
dc.format.extent3966207 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2006 ICS會議
dc.subject.otherCircuit Design
dc.titleTFT-LCD Timing Control Based on FPGA
分類:2006年 ICS 國際計算機會議

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