完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | 蔡宗翰 | |
dc.contributor.author | 謝益倫 | |
dc.contributor.author | 陳恩禎 | |
dc.date | 94學年度 | |
dc.date | 第一學期 | |
dc.date.accessioned | 2009-06-03T03:19:50Z | |
dc.date.accessioned | 2020-05-22T08:32:08Z | - |
dc.date.available | 2009-06-03T03:19:50Z | |
dc.date.available | 2020-05-22T08:32:08Z | - |
dc.date.issued | 2007-11-06T02:02:13Z | |
dc.identifier.other | D9342019、D9056084、D9145256 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/526 | - |
dc.description.abstract | 近來,由於低溫複晶矽薄膜電晶體應用於主動式陣列顯示器因而漸漸受到注意及歡迎,如LCD及OLEDs元件,藉由高可靠度低溫複晶矽薄膜電晶體,積體電路整合於同一面板(SOG)便可以有效實現,而高可靠度低溫複晶矽薄膜電晶體的便是要求高驅動電流能力以及低漏電流的特性。 不幸的是,我們發現傳統TFT元件有一些負面的影響,由於有較大漏電流、扭結效應、熱載子效應,使元件特性不佳、可靠度降低,嚴重限制了前述的發展,因此,如何提升低溫複晶矽薄膜電晶體的效能是非常重要的。 大部分負面不良影響大致來自於通道與接面處高電場的現象,也就是說,降低其大電場即可有有效抑制那些不好的效應。已經有很多文獻提出很多結構可以有效降低汲極電場。但是,那些結構往往需要額許多外製程的幫助,例如離子佈植、側間隔及多道光阻數目的幫助。 在此報告中,我們嘗試提出新穎降電場結構,稱作為:”閘極覆蓋輕摻雜汲極端雙閘極低溫複晶矽薄膜電晶體結構”,此結構製程簡單且不需額外的光罩及額外的離子佈植。我們透過ISETCAD元件製程模擬軟體實際驗證及模擬分析。此結構可有效降低汲極端高電場現象。 | |
dc.description.abstract | Recently, low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFTs) have become attractive and popular due to their applications in active-matrix displays,such as LCD and OLED devices. Active matrix displays with integrated circuits in a single panel substrate can be implemented by high-performance LTPS TFTs. The requirements for high-performance device are high current-driving capability together with low leakage current characteristics. Unfortunately, we found the undesired side-effects of conventional TFTs device operation, including large leakage currents, kink effects, and hot-carrier effects, thus limiting the device performance. Therefore, intention to improve the LTPS-TFT device performance is the motive for this work. All the undesired effects are mainly caused by the high electric field near the drain regime. Therefore, how to effectively reduce the electric field by maintaining device performance is an important issue to resolve in this work. Extensive studies have reported various structures that can effectively reduce the channel electric field near the drain region. However, additional and complicated device processings are required in those proposed structures, including hydrogen implantations and the spacer formation. These will tremendously complicate the sequences lithography procedures. In this work, we proposed a novel structure to effectively relieve the electric field. It is called the “Gate-Overlapped Lightly-Doped Drain Polycrystalline Silicon Thin-Film Transistor with a Double-Gate Structure”. This structure is effective with simple fabrication process requirement. We have successfully demonstrated and verified with the ISE-TCAD simulation. | |
dc.format.extent | 61 | |
dc.format.extent | 1090224 bytes | |
dc.format.extent | 1832 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language | 中文 | |
dc.language.iso | zh_TW | |
dc.rights | 開放檢索瀏覽下載 | |
dc.title | 以新穎降電場結構改善低溫複晶矽薄膜電晶體特性研究 | |
dc.title | Study on the Novel Drain-Relief Structures in Low-Temperature Polycrystalline Silicon Thin Film Transistor to Improve the Device Characteristics | |
dc.type | 大學生專題報告 | |
dc.description.course | 化合物半導體 | |
dc.contributor.department | 電子工程學系,資訊電機學院 | |
dc.description.instructor | 李景松 | |
dc.description.programme | 資訊電機學院 | |
dc.description.programme | 電子工程學系半導體學程 | |
分類: | 資電094學年度 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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D9145256200501.pdf | 1.06 MB | Adobe PDF | 檢視/開啟 |
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