瀏覽 的方式： 作者 Shiau, Yeu-Horng
顯示 1 到 6 筆資料，總共 6 筆
| 題名 | 作者 | 日期 |
| A Tree-Block Scheduling Architecture for Separable 2-D Inverse Discrete Wavelet Transform | Shiau, Yeu-Horng; Jou, Jer-Min | 2006-11-16T03:31:41Z |
| An Integrated MAC IP Design for IEEE 1394 and Ethernet | Chen, Yu-Chia; Shiau, Yeu-Horng; Kuang, Shiann-Rong; Jou, Jer-Min | 2006-10-16T01:38:56Z |
| Bus Wrapper Design Methodology in SoC | Wu, Kuang-Li; Jou, Jer-Min; Shiau, Yeu-Horng | 2006-10-16T03:39:35Z |
| Design of a Network Layer Protocol Transformer Between IP and ATM | Lin, Tzeng-Yi; Shiau, Yeu-Horng; Kuang, Shiann-Rong; Jou, Jer-Min | 2006-10-16T01:39:09Z |
| Design of Modular Scalable HMM-based Continuous Speech Recognition / Convolutional Decoder IP | Shiau, Yeu-Horng; Jou, Jer-Min; Wang, Tsung-Chih | 2006-10-23T15:33:40Z |
| Hierarchical Interface Design Methodology: Using Real-Time MP3 codec as a case | Jun-Sheng Zheng; Shiau, Yeu-Horng; Jou, Jer-Min | 2006-10-23T15:34:03Z |
