題名: 具雙重執行模式之單晶片多處理機架構
作者: 伍朝欽
關鍵字: Chip-Multiprocessor
Superscalar Processor
Multithreaded Architecture
Speculative Execution
Instruction-Level Parallelism.
期刊名/會議名稱: 中華民國92年全國計算機會議
摘要: Previous research show that, chip-multiprocessors have better speedup for floating-point-operation-intensive benchmark programs but worse for integer- operation-intensive application programs when compared with superscalar architectures. In this paper, we propose a novel microprocessor, combining the advantages of superscalar and chip-multiprocessor architectures, to provide the best performance regardless of workload types. Our architecture has two execution modes: one for multithreads and one for single thread. The new CPU can issue and execute sixteen instructions during each cycle regardless of the execution mode. In the first mode, the system behaves like a conventional chip-multiprocessor. On the other hand, we integrated separate four processing elements into a single logical superscalar processor in the second mode. When executing a program, the architecture keeps switching between two execution modes according to the feature of the subsequent codes to be run.
日期: 2006-06-15T03:20:01Z
分類:2003年 NCS 全國計算機會議

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