Design of Message Authentication Code with AES and SHA-1 on FPGA

Abstract

Combining AES 128-bit and SHA-1, we construct a Message Authentication Code and implement it on Altera FPGA chip. We use the math of finite-field in AES algorithm to reduce the complexity of AES module. Implementation of our architecture needs 17153 logic cell elements on an FPGA chip. The performance achieves 12.4 MHz in frequency. Moreover, the proposed design architecture does not require any memory bits.