Design of A Reconfigurable Floating-Point Unit

Abstract

In this paper, we propose a reconfigurable floating-point unit architecture that has higher performance and flexible than the traditional integer and floating-point arithmetic unit. It can perform 8-bit, 16-bit, 24-bit and 32-bit signed/unsigned integer multiplication, and perform 8-bit, 16-bit, 32-bit and 64-bit add/sub adder. For floating-point operations, it can perform IEEE standard single precision floating-point add/sub/mul operations. For integer operations, we use “single instruction multiple data” (SIMD) technology to perform a lot of lower bit width of operands at the same operation. The proposed reconfigurable arithmetic unit can be used as a co-processing unit or an arithmetic unit in general-propose processors. The experimental result indicated that the maximum operation frequency of proposed reconfigurable arithmetic unit is 309MHz.