Improved Context Modeling Architecture of JPEG2000 on FPGA

Abstract

In this paper, an improved context modeling architecture of JPEG2000 implemented on FPGA is proposed. The proposed architecture is based on a pass-pipelined structure with dual memories and data multiplexer. The proposed context modeling architecture allows multiple symbol context pairs to be generated simultaneously while the pass-pipelined structure helps to reduce the processing time and the critical path delay. Moreover, the dual memories and data multiplexer are employed in order to accelerate the memory access. The proposed passpipelined architecture can process with the speed greater than 100 MHz and can generate up to 22 context-data pairs in one clock cycle.